The use of electronic circuits such as microcontrollers to produce periodic signals (for example pulse-width modulated signals, ignition pulses, etc.) is of increasing importance. In general the signal characteristics may be changed during operation of the circuits. In prior devices, an internal timer is used to establish the time of an action. To this end, a value is stored in a comparison register that is compared with the internal timer. If a new value is now programmed into the comparison register, this new value can lie in the past from the point of view of the timer, but the overwritten value still exists in the future. When this happens, the write operation during the current period does not execute an action. The result is in an entirely disrupted signal (the signal has a “1” signal or “0” signal over a period).
Some prior devices allow changes of the contents of the comparison register only at specific time points which are not complicated for the signal. In general, the time points occur directly after an action. To this end, the unit that changes the contents of the comparison register must either wait for the right time point in a wait loop, or an interrupt (i.e. a program interruption request) activates this unit, which then updates the contents of the comparison register in an interrupt handling routine. If there is only a short time window between the old action and the new action, the program could be delayed by the interrupt's latency period or by the limited performance of the unit such that the new value occurs only after the targeted time period. When that happens, the result is a false signal (a period 0% or 100% signal). Moreover, wait loops and interrupt handling result in significant losses of performance for the unit that updates the comparison data. Furthermore, the generation of a new signal is significantly delayed in some circumstances.
A complex set of instructions may be used to alleviate the above disadvantages. However, it is not possible to completely avoid all cases since non-deterministic behavior (bus allocation, other interrupts, etc.) make timely processing much more difficult. In yet a further prior device, a stacking memory (FIFO) is used. The comparison register is used multiple times. After a successful comparison action, the contents of the register last written to are transferred to the comparison register. Thus, in all cases only the previous and the current signal are generated. This method has a disadvantage that the generation of a new signal is delayed in some cases since first an old event must take place. This can in some cases result in a complete malfunction if the old value corresponds to a deactivation (for example to produce a pulse width modulation of 0% or 100%). Another disadvantage is the hardware expense and inflexibility of use of the hardware, since the multiple implementation of the comparison register can only be used for the controlled change between two signals and can not be freely allocated by other timer channels.
A still further prior device uses identical modules to produce temporal signals. Many of these modules can produce a signal together. To do so, these modules are connected to a signal output module via a bus. Various commands can now be transmitted on this bus, for example signal transition from “0” to “1”, from “1” to “0”, changing the state dependent on the current state or suppression of a signal from another unit. This bus is constructed hierarchically (sequentially) so that all units are connected one after the other on the bus. The superior command (i.e. further forward in the chain) is overwritten by an inferior command that is issued at the same time. An additional line now permits a series of modules to together deactivate and activate at a period limit. Thus, a portion of the cells can be configured such that they are used to configure the new data. After updating all of these registers, the change to the next period limit is activated. This method has the disadvantage that the generation of a new signal may be significantly delayed, since first an old event must take place. Moreover, all updates must be done simultaneously since after writing new register contents and activation of the change at the next period limit for another update, for example of another set of registers, one has to wait for the period limit or temporarily deactivate the update risking to miss the next period limit and in case of periodical deactivating missing all updates.